1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) having a structure provided with a memory cell including six metal oxide semiconductor (MOS) transistors (hereinafter, referred to as a “full CMOS cell”) and enabling improvement of soft-error tolerance.
2. Description of the Background Art
With development of lower-voltage SRAM, an SRAM provided with full CMOS cells each including six MOS transistors (hereinafter, referred to as a “full CMOS SRAM”) has become dominant.
Generally, a full CMOS cell is formed of two bulk access n-MOS transistors, two bulk driver n-MOS transistors and two bulk load p-MOS transistors.
The full CMOS cell exhibits relatively good soft-error tolerance. With downsizing of design rules, however, the cell size of the SRAM memory cell has increasingly been reduced. With lowering of the voltage, the charges (voltage×capacitance) accumulated in storage nodes of the SRAM memory cell have decreased, making a soft error a serious problem. As a result, in an SRAM operating with low voltage, it has become necessary to address such soft errors, even in the case of the full CMOS SRAM.
The soft error refers to a phenomenon in which data having been held is inverted for some reasons, which may include, for example, a noise due to an electron-hole pair that is generated when an α ray emitted from uranium (U) or thorium (Th) included in a package passes through a silicon substrate.
As the way of addressing the soft errors, for example, capacitance may be added to the storage nodes in an SRAM.
SRAM provided with such measures are described, for example, in Japanese Patent Laying-Open Nos. 06-151771 (conventional example 1) and 2002-083882 (conventional example 2).
The conventional example 1 discloses an SRAM wherein capacitor electrodes form two capacitors cross-coupled between gates of drive transistors.
The conventional example 2 discloses an SRAM wherein a flip-flop circuit is formed by cross-connecting mutual input/output terminals (storage nodes) of a pair of CMOS inverters via a pair of local interconnections, with capacitance being formed between each local interconnection and a reference voltage line.
In Japanese Patent Laying-Open No. 2002-076143 (conventional example 3), an SRAM is disclosed wherein local interconnections have their surfaces roughened to ensure large capacitance of the capacitor formed between local interconnections.
The above-described SRAM, however, suffer the following problem.
When capacitance is being added by the capacitor as described above, if the capacitor is increased in size to secure certain capacitance, the cell size will increase. That is, in order to improve the soft-error tolerance, a structure that will not place an obstacle to reduction of the cell area needs to be employed.
Any of the conventional SRAM memory cells as described above do not have a structure suitable for a lateral type cell in which three partitioned wells are arranged side by side in the direction along which a word line extends.